The present invention is directed to integrated circuits. More particularly, the invention provides a system and method for reducing standby power consumption. Merely by way of example, the invention has been applied to a power converter. But it would be recognized that the invention has a much broader range of applicability.
Power converters are widely used for consumer electronics such as portable devices. The power converters can convert electric power from one form to another form. As an example, the electric power is transformed from alternate current (AC) to direct current (DC), from DC to AC, from AC to AC, or from DC to DC. Additionally, the power converters can convert the electric power from one voltage level to another voltage level.
The power converters include linear converters and switch-mode converters. The switch-mode converters often have higher efficiency than the linear converters. Additionally, the switch-mode converters usually use pulse-width-modulated (PWM) or pulse-frequency-modulated (PFM) mechanisms. Moreover, a PWM switch-mode converter can be either an offline flyback converter or a forward converter.
The switch-mode converters can consume significant power under standby conditions, such as with light or zero output loads. But the switch-mode converters need to meet various international standards concerning energy saving, such as requirements for Energy Star or Blue Angel. Therefore, the switch-mode converters should have low standby power consumption and high power efficiency under light or no load conditions. The no load conditions include, for example, standby, suspend or some other idle conditions. In another example, the standby power consumption includes energy losses at various components of the switch-mode converters such as power switches, transformers, inductors, and snubbers. These losses often increase with the switching frequency.
To reduce the standby power, the switching frequency is usually lowered for light or zero output loads. But if the switching frequency becomes too low and falls within the audio range, unwanted audible noises arise. One way to avoid these audible noises but also reduce standby power is to operate the switch-mode converters in the burst mode. In the burst mode, from time to time, some PWM cycles are skipped and the operation can become asynchronous depending on the load conditions.
FIG. 1(A) is a simplified diagram showing a conventional off-line flyback converter. The converter 100 includes a chip 110 for PWM control, a power switch 120, a primary winding 130, a secondary winding 132, an auxiliary winding 134, diodes 140, 142, and 144, capacitors 150, 152 and 154, resistors 160, 162, 164 and 166, an isolated feedback component 170, an electromagnetic interference filter 180, and an input rectifier and filter component 182.
FIG. 1(B) is a simplified diagram showing the conventional chip 110 for PWM control. The chip 110 for PWM control includes a PWM controller component 220, a gate driver 230, an oscillator 240, a protection component 242, a current and voltage generator 244, a leading-edge-blanking component 246, and an over-current comparator 248. Also, the chip 110 for PWM control includes terminals 112, 114, 116, and 118. For example, the PWM controller component 220 includes a PWM comparator 222 and a logic controller 224. In another example, the protection component 242 includes one or more components for over-voltage protection, over-temperature protection, over-current protection (OCP), and/or over-power protection (OPP). In yet another example, the current and voltage generator 244 is configured to generate one or more voltages and/or one or more currents.
FIG. 1(C) is a simplified diagram showing the conventional isolated feedback component 170. The isolated feedback component 170 includes resistors 172, 173 and 174, a capacitor 175, an error amplifier 176, and a photo coupler 178 that includes a photodiode 184 and a phototransistor 186.
Referring to FIG. 1(A) and FIG. 1(B), the converter 100 provides an output voltage 199 (e.g., Vo) and an output current (e.g., Io) to an output load 168, such as an output resistor. In more detail, the PWM controller component 220 generates a PWM signal 232, which is received by the gate driver 230. In response, the gate driver 230 sends a gate signal 192 to the power switch 120 through the terminal 112. Accordingly, the power switch 120 adjusts the current 122 flowing through the primary winding 130. For example, if the power switch 120 is turned on, the power switch 120 is closed, allowing the current 122 to flow through the primary winding 130. In another example, if the power switch is turned off, the power switch 120 is open, thus not allowing the current 122 to flow through the primary winding 130.
The current 122 is sensed by the resistor 166 and converted into a current sensing signal 194 (e.g., Vcs) through the terminal 114 and the leading-edge-blanking component 246. The current sensing signal 194 is received by the OCP comparator 248 and compared with an over-current threshold signal 195 (e.g., Vth—oc). In response, the OCP comparator 248 sends an over-current control signal 249 to the logic controller 224. When the current of the primary winding is greater than a limiting level, the PWM controller component 220 turns off the power switch 120 and shuts down the switch-mode power converter 100, thus limiting the current 122 flowing through the primary winding 130 and protecting the switch-mode power converter 100.
As shown in FIG. 1(A), FIG. 1(B) and FIG. 1(C), the output voltage 199 (e.g., Vo) of the secondary winding 132 is sensed by the isolated feedback component 170. In response, the isolated feedback component 170 sends a feedback signal 198 (e.g., VFB) to the PWM comparator 222 through the terminal 118. The PWM comparator 222 also receives the current sensing signal 194 and generates a PWM comparator output signal 223. The PWM comparator output signal 223 is received by the logic controller 224, which generates the PWM signal 232 based on at least information associated with the PWM comparator output signal 223.
The chip 110 for PWM control is powered by the auxiliary winding 134, the diode 140, the capacitor 150, and the resistor 160 through the terminal 116. When the power switch 120 is turned on, the energy is taken from the input and stored in the primary winding 130. Also, the diode 144 is reverse biased, thus the output load 168 is powered by the energy stored in the capacitor 154.
When the power switch 120 is turned off, some energy stored in the primary winding 130 is transferred to the secondary winding 132 that is coupled to the primary winding 130. Consequently, the diode 144 becomes forward-biased, and the energy is delivered to the capacitor 154 and to the output load 168. The output voltage 199 (e.g., Vo) is also reflected back to the primary winding 130, causing an increase of the drain voltage of the power switch 120 that includes a field effect transistor (FET).
Additionally, when the power switch 120 is turned off, the energy stored in the primary winding 130 is also transferred to the auxiliary winding 134 that is coupled to the primary winding 130. Consequently, the diode 140 becomes forward biased, and some energy stored in the primary winding is delivered to the capacitor 150 and used to provide a chip supply voltage 196 (e.g., VDD) to the chip 110 through the terminal 116. The combination of the auxiliary winding 134, the diode 140, the capacitor 150, and the resistor 160 is called the self-supply circuit.
FIG. 2 is a simplified conventional diagram showing burst mode operation for the converter 100. The waveform 202 represents the output voltage 199 (e.g., Vo) as a function of time, the waveform 204 represents the feedback signal 198 as a function of time, the waveform 206 represents the current 122 that flows through the power switch 120 as a function of time, and the waveform 208 represents a drain-source voltage of the power switch 120 that includes a FET.
As shown in FIG. 2, Ton is the burst-on time, and Toff is the burst-off time. During Ton, the drive signal 192 turns on and off the power switch 120 at a switching frequency that is above an audio frequency range, and during Toff, the power switch 120 remains being turned off. Also, Tburst denotes the burst period that is equal to Ton plus Toff, and Ton/Tburst represents the burst duty cycle. For example, the burst period depends on the load conditions. In another example, the burst duty cycle is reduced in order to lower the standby power at a given switching frequency. Specifically, the standby power can be lowered by reducing the burst-on time and/or increasing the burst-off time.
But the burst-on time and the burst-off time can also be constrained by the current consumption of the chip 110 for PWM control. Referring to FIG. 1(A), the output voltage 199 (e.g., Vo) and the chip supply voltage 196 (e.g., VDD) are related to each other as follows:
                              V          DD                =                                                                              V                  o                                ⁢                                  V                  fb                                                            N                s                                      ×                          N              a                                -                      V            fa                                              (                  Equation          ⁢                                          ⁢          1                )            where Ns and Na represent the number of turns of the secondary winding 132 and the number of turns of the auxiliary winding 134 respectively. Additionally, Vfa and Vfb represent the forward voltage of the diode 140 and the forward voltage of the diode 144 respectively. According to Equation 1, the chip supply voltage 196 (e.g., VDD) increases with the increasing output voltage 199 (e.g., Vo), and decreases with the decreasing output voltage 199 (e.g., Vo).
Referring to FIG. 2, during Toff, the power switch 120 is turned off, causing both the output voltage 199 (e.g., Vo) and the chip supply voltage 196 (e.g., VDD) to drop. If the chip supply voltage 196 (e.g., VDD) becomes smaller than the under-voltage lockout (UVLO) threshold, the chip 110 for PWM control is powered off. Subsequently, a start-up process is initiated. Often, the start-up process can take several seconds, during which, the output voltage 199 (e.g., Vo) becomes out of regulation and hence falls off.
Therefore, to maintain the output regulation, it is important to keep the chip supply voltage 196 (e.g., VDD) above the UVLO threshold, and the burst duty cycle Ton/Tburst also above a minimum level. The minimum level of the burse duty cycle is used to maintain the appropriate balance between charging and discharging of the capacitor 150 in order to keep the chip supply voltage 196 (e.g., VDD) above the UVLO threshold.
FIG. 3 is a simplified conventional diagram showing a relationship between the chip supply voltage 196 (e.g., VDD) and the output voltage 199 (e.g., Vo) under different load conditions. In Region C, under normal and heavy load conditions, the chip supply voltage 196 (e.g., VDD) drifts higher since the charging of the capacitor 150 is stronger than the discharging of the capacitor 150. In contrast, in Region A, under no load conditions, the chip supply voltage 196 (e.g., VDD) drifts lower since the charging of the capacitor 150 is weaker than the discharging of the capacitor 150. Furthermore, the chip supply voltage 196 (e.g., VDD) may drop further below the UVLO threshold, and thus enter into Region D. Then, the chip 110 for PWM control is powered down, hence no switching is performed, and no energy is delivered to the output load 168 or the capacitor 150.
Afterwards, the capacitor 150 is recharged through the resistor 162. If the chip supply voltage VDD rises above a start-up threshold, the chip 110 for PWM control resumes operations as shown by Region A. But if the charging of the capacitor 150 remains weak, the chip supply voltage 196 (e.g., VDD) can again fall below the UVLO threshold, as shown by Region D. Consequently, the converter 100 ends up changing back and forth between Region A and Region D. The output of the converter 100 remains out of regulation, and no regulated output voltage can be obtained.
Referring to FIG. 1(A) and FIG. 1(B), the output regulation is accomplished through the isolated feedback component 170. The isolated feedback component 170 receives the output voltage 199 (e.g., Vo) and sends the feedback signal 198 to the chip 110 through the terminal 118. The feedback signal 198 represents the output voltage 199 (e.g., Vo). Hence the drive signal 192 with PWM modulation is controlled by at least the feedback signal 198 in order to regulate the output voltage 199 (e.g., Vo) to the desired voltage level.
In contrast, the chip supply voltage 196 (e.g., VDD) is not regulated. The variation in the chip supply voltage 196 is not corrected through any feedback loop. To keep the chip supply voltage 196 above the UVLO threshold, a dummy load often is added to the output of the converter 100 in order to maintain the output regulation even under no load conditions. But the dummy load consumes a constant power and hence degrades the power efficiency of the converter 100, especially under light or no load conditions.
Hence it is highly desirable to improve the techniques for reducing standby power consumption.